Hardware threads processor core utilization

ABSTRACT

A determination of processor core utilization by a plurality of hardware threads over a time interval is made through a division of a length of the time interval by a total count of the plurality of hardware threads.

BACKGROUND

Multithreaded hardware computer architecture may have an Interval Timer Counter (ITC) shared by two or more hardware threads on a same processor core, for example, a CPU (central processing unit) core. The ITC advances irrespective of which hardware thread is executing on the processor core. An operating system (OS) for the processor core has no control over context switch events of the hardware threads. For example, an operation available to the hardware threads comprises a simple yield instruction such as hint@pause or PAL_HALT_LIGHT. Measurements are not performed on a per-hardware thread basis. An inability to accurately measure core execution time and core utilization from algorithms based on the ITC result in a double counting of execution time and a doubling of core utilization metrics, for example, for two hardware threads.

DESCRIPTION OF THE DRAWINGS

Features of exemplary implementations of the invention will become apparent from the description, the claims, and the accompanying drawings in which:

FIG. 1 is a representation of an implementation of an apparatus that comprises a computer that comprises a processor core, a plurality of memory locations, one or more I/O (input/output) devices, and one or more interconnectors, and illustrates exemplary memory with an exemplary operating system (OS) that comprises an exemplary scheduler according to a preferred embodiment of the invention.

FIG. 2 is an exemplary functional block diagram that comprises the exemplary scheduler of the exemplary operating system (OS), and illustrates exemplary output of a determination of a plurality of actual hardware thread execution and core utilization times for a respective plurality of hardware threads that processes a plurality of software threads from a task queue on the processor core of an implementation of the apparatus of FIG. 1.

FIG. 3 is a representation of an exemplary flow of utilization of the processor core between exemplary hardware threads of an implementation of the apparatus of FIG. 1.

FIG. 4 is a representation of an exemplary logic flow for determination of hardware thread core execution time and core utilization between OS context switches on an implementation of the apparatus of FIG. 1.

FIG. 5 is similar to FIG. 4 and further employs timer measurements, adjustment time counters, and yield operation time.

DETAILED DESCRIPTION

Referring to the BACKGROUND section above, a computer architecture such as an exemplary multithreaded hardware architecture with an Interval Timer Counter (ITC) shared by two or more hardware threads on the same processor core, lacks an ability to acceptably, desirably, and/or accurately account for actual time of core execution and core utilization by each hardware thread. Exemplary causes comprise the ITC advancement irrespective of which hardware thread is executing on the processor core, for example, CPU (central processing unit) core, and/or the randomness of hardware thread context switching. An exemplary operating system (OS) for the processor core has little or no control over context switch events of the hardware threads.

An exemplary approach divides the time of execution of the hardware threads by the total number of hardware threads to make a determination of execution time per hardware thread. The time of execution may comprise the time accumulated in the ITC for machines that do not have a per-hardware thread ITC that would otherwise accumulate time only when a particular hardware thread is executing.

An exemplary operation available to the hardware threads comprises a yield instruction, for example, hint@pause or PAL_HALT_LIGHT. When a hardware thread performs a yield operation, the yielding hardware thread in an example is incorrectly charged for execution time on the core during the yield operation. The other hardware thread that received utilization of the core in an example is charged only for a portion of the time it actually consumed. The yield operations on exemplary multithreaded hardware cause inaccuracies in measuring how much time a hardware thread consumed a processor core.

An exemplary implementation charges back to the receiving hardware thread on the processor core, the time spent in the yield operation, for example, to increase and/or improve accuracy in time accounting. An exemplary implementation accounts for the time a hardware thread spends in a yield operation to obtain actual core execution time and core utilization for both the yielding and receiving hardware threads. An exemplary implementation employs a running execution time counter and an adjustment factor counter for each hardware thread.

When a hardware thread executes a yield operation, the hardware thread in an example stores the current time value. When the hardware thread resumes execution, the hardware thread in an example subtracts the previously saved time value from the updated current time value to determine the time that was spent while yielding to the other hardware thread. An exemplary implementation arranges to subtract the yielding time from an execution time count for the yielding hardware thread, and add the yielding time to an execution time count for the receiving hardware thread.

An exemplary implementation subtracts the yielding time from an adjustment factor counter for the yielding hardware thread, and adds the yielding time to the adjustment factor counter for the receiving hardware thread. An exemplary implementation employs the adjustment factor counters to calculate the core execution time and core utilization for the yielding and receiving hardware threads. When each hardware thread calculates its own time accounting and core utilization for the task it is running, the hardware thread in an example adds the adjustment factor counter to the running execution time counter to determine the actual execution time. An exemplary implementation increases and/or improves accuracy in time accounting when multithreaded hardware yield operations are allowed.

Turning to FIG. 1, an implementation of an apparatus 100 in an example comprises one or more computers, computer systems, and/or computing devices. An exemplary implementation comprises a computer 102 that comprises a processor core and/or core resource 104, a plurality of memory locations and/or disk drives such as one or more of memory 106 and/or storage 108, one or more I/O (input/output) devices 110, and one or more interconnectors 112. An exemplary processor core 104 comprises an interval timer counter (ITC) 114. An exemplary memory 106 is employable to store programs and data during operation of the computer 102. The memory 106 in an example serves to store an operating system (OS) 116 that comprises a scheduler 118. An exemplary interconnector 112 serves to couple components of the computer 102. The interconnector 112 in an example may comprise one or more busses and/or networks, for example, to enable communications to be exchanged between components of the computer 102.

One or more components of the apparatus 100 and/or the scheduler 118 comprise an exemplary implementation of an algorithm, procedure, program, mechanism, engine, model, coordinator, module, application, code, and/or logic. An exemplary component may be implemented as kernel-resident and/or operating-system-resident logic and/or may comprise user-level programs, for example, user interface logic residing in user-level program files with additional and/or remaining logic residing in the kernel and/or underlying operating system.

Turning to FIG. 2, the scheduler 118 in an example comprises one or more components, for example, a context switch engine 202, a hardware thread execution time measurer 204, an idle/yield engine 206, a hardware thread yield time measurer 208, and/or a processor core and hardware thread utilization and execution measurement engine and/or utilization measuring facility 210. The hardware thread execution time measurer 204 and/or the hardware thread yield time measurer 208 in an example comprise a running execution time counter. The processor core and hardware thread utilization and execution measurement engine 210 in an example comprises one or more components, for example, an execution time counter 212, an ITC adjustment engine 214, an idle/yield time counter 216, and/or a utilization summary engine 218. An exemplary processor core and hardware thread utilization and execution measurement engine 210 outputs a determination of a plurality of actual hardware thread execution and core utilization times, for example, actual hardware thread execution and core utilization times 220, 222, 224 for a respective plurality of hardware threads, for example, hardware threads 226, 228, 230 on the processor core 104.

The hardware threads 226, 228, 230 in an example independently and/or substantially simultaneously process a plurality of software threads contained in a task queue 234. An exemplary implementation of task queues 234 comprises a respective task queue 234 for each hardware thread 226, 228, 230. The hardware thread 226 in an example processes a set of the software threads 238 followed by zero or more additional software threads of the plurality of software threads 238. The hardware thread 228 in an example processes a set of the software threads 240 followed by zero or more additional software threads of the plurality of software threads 240. The hardware thread 230 in an example processes a set of the software threads 242 followed by zero or more additional software threads of the plurality of software threads 242.

An exemplary OS scheduler 118 comprises the task queue 234, the context switch engine 202, and the utilization measuring facility 210. The task queue 234 in an example maintains the available software thread 238, 240 242 to be executed on the hardware threads 226, 228, 230. The context switch engine 202 in an example controls which software thread 238, 240, 242 executes on which hardware thread, 226, 228, 230. The idle engine 206 in an example performs yield operations when the hardware thread 226, 228, 230 is not utilizing the core resource 104.

The utilization measuring facility 210 in an example maintains and calculates the utilization of hardware resources. The utilizing measuring facility 210 in an example comprises the execution time counter 212, the adjustment engine 214 based on number of hardware threads 226, 228, 230, and the idle/yield time counter 216 that provides the interval time of idling or yielding. An exemplary summary of hardware thread utilization of the core resource 104 is summarized by the utilization summary engine 218, for example, by calculation based on a formula that employs information, output, and/or data from the execution time counter 212, the adjustment engine 214 based on number of hardware threads 226, 228, 230, and the idle/yield time counter 216. The utilization measuring facility 210 outputs hardware threads utilization 220, 222, 224.

In one or more exemplary implementations, one or more features described herein in connection with one or more of the hardware threads 226, 228, and/or 230 and/or one or more parts thereof apply and/or are extendible analogously to one or more of the others and/or one or more other instances of hardware threads in the apparatus 100.

Turning to FIG. 3, an exemplary flow 302 of utilization of the processor core 104 may occur between exemplary hardware threads 226, 228. An exemplary hardware thread 226, 228 may share utilization of the processor core 104. The hardware thread 226, 228 in an example receives use of the processor core 104 in amounts, slices, and/or lengths 304 of time. The length 304 of time of utilization of the processor core 104 by an exemplary hardware thread 226, 228 may vary. An exemplary implementation may initially offer a uniform length 304 of time switched among a plurality of hardware threads 226, 228. Another exemplary implementation may initially offer a non-uniform length 304 of time switched among each, sets, or all of a plurality of hardware threads 226, 228. The hardware threads 226, 228 in an example may perform yield operations, for example, that change the actual length 304 of time from the initial allocation preliminarily scheduled and/or set, for example, by the hardware or the operating system (OS) 116.

An exemplary “Yield Operation Start” on the flow 302 comprises a start time when a hardware thread 226, 228 executes one of the yield operations. An exemplary “Yield Operation End” on the flow 302 comprises an end or completion that the hardware thread 226, 228 executes the yield operation. Other end points on the flow 302 comprise occurrences of a normal hardware thread context switch.

An illustrative description of a number of exemplary operations of an implementation of the apparatus 100 is presented, for explanatory purposes. FIG. 4 is a representation of an exemplary logic flow 402 for determination of hardware thread core execution time and core utilization between OS context switches. Referring to FIGS. 3 and 4, in exemplary logic flow 402 at STEP 404, the OS scheduler 118 schedules software threads 232 into the task queue 234. At STEP 406 in an example the hardware thread execution time measurer 204 reads the ITC 114 for each hardware thread 226, 228, 230. At STEP 408 in an example the context switch engine 202 starts executing each software thread 238, 240, 242 scheduled on each hardware thread 226, 228, 230. At STEP 410 in an example the context switch engine 202 stops execution. The hardware thread execution time measurer 204 in an example reads the ITC 114 for each hardware thread 226, 228, 230. At STEP 412 in an example the processor core and hardware thread utilization and execution measurement engine 210 determines execution time and core utilization for each hardware thread 226, 228, 230. An exemplary processor core and hardware thread utilization and execution measurement engine 210 determines the start and stop execution time from the execution time counter 212 and adjusts for the number of hardware threads 226, 228, 230 on the interval time counter (ITC) adjustment engine 214 for the processor core 104. At STEP 414 in an example the context switch engine 202 switches out the software threads 232 from each hardware thread 226, 228, 230.

FIG. 5 is a representation of an exemplary logic flow 502 for determination of hardware thread core execution time and core utilization between OS context switches based on timer measurements, adjustment time counters, and yield operation time. Referring to FIGS. 3 and 5, in exemplary logic flow 502 at STEP 504, the OS scheduler 118 schedules software threads 232 into the task queue 234. At STEP 506 in an example the hardware thread execution time measurer 204 reads the ITC 114 for each hardware thread 226, 228, 230. At STEP 508 in an example the context switch engine 202 starts executing each software thread 238, 240, 242 scheduled on each hardware thread 226, 228, 230. At STEP 510 in an example the idle/yield engine 206 determines the amount of time the hardware thread 226 yielded execution to another hardware thread 228 as measured by the hardware thread yield time measurer 208. At STEP 512 in an example the context switch engine 202 stops execution. The hardware thread execution time measurer 204 in an example reads the ITC 114 for each hardware thread 226, 228, 230. At STEP 514 in an example the processor core and hardware thread utilization and execution measurement engine 210 determines execution time and core utilization for each hardware thread 226, 228, 230. An exemplary processor core and hardware thread utilization and execution measurement engine 210 determines the start and stop execution time from the execution time counter 212, adjusts for the number of hardware threads 226, 228, 230 on the interval time counter (ITC) adjustment engine 214 for the processor core 104, and adjusts for yield time by each hardware thread 226, 228, 230 in the idle/yield time counter 216 and calculated by the utilization summary engine 218. At STEP 516 in an example the context switch engine 202 switches out the software threads 232 from each hardware thread 226, 228, 230.

An exemplary approach makes a determination of processor core utilization 220, 222, 224 by a plurality of hardware threads 226, 228, 230 over a time interval through a division of a length of the time interval by a total count of the plurality of hardware threads 226, 228, 230.

One or more hardware thread context switches among two or more of the plurality of hardware threads 226, 228, 230 occur over the time interval. A result of the division of the time interval by the total count of the plurality of hardware threads 226, 228, 230 is interpreted as a per-thread processor core utilization 220, 222, 224.

The total count comprises a total count of the plurality of hardware threads 226, 228, 230 on a single processor core 104. One or more hardware thread context switches for utilization of the single processor core 104 occur among two or more of the plurality of hardware threads 226, 228, 230 over the time interval. A determination of utilization of the single processor core 104 by the plurality of hardware threads 226, 228, 230 over the time interval is made through the division of the time interval by the total count of the plurality of hardware threads 226, 228, 230.

The plurality of hardware threads 226, 228, 230 comprises at least a first hardware thread and a second hardware thread of two hardware threads 226, 228, 230 on a single processor core 104. A determination of utilization of the single processor core 104 by the two hardware threads 226, 228, 230 over the time interval is made through division of the time interval by two. At least a first software thread is processed independently by the first hardware thread during the time interval. At least a second software thread is processed independently by the second hardware thread during the time interval.

The total count comprises a total count of the plurality of hardware threads 226, 228, 230 on an operating system (OS) 116 for a single processor core 104. The time interval occurs between successive OS context switches of the OS 116. One or more hardware thread context switches for utilization of the single processor core 104 occur among two or more of the plurality of hardware threads 226, 228, 230 over the time interval. A determination of processor core utilization 220, 222, 224 by the plurality of hardware threads 226, 228, 230 between the successive OS context switches and over the one or more hardware thread context switches is made through a division of the length of time between the successive OS context switches by the total count of the plurality of hardware threads 226, 228, 230 on the OS 116 of the single processor core 104.

One or more hardware thread context switches among two or more of the plurality of hardware threads 226, 228, 230 occur over the time interval. The length of the time interval is divided by the total count of the plurality of hardware threads 226, 228, 230 to make the determination of processor core utilization 220, 222, 224 as a substitute for employment of one or more absent, unselected, and/or unavailable per-hardware thread interval time counters that would otherwise be employable to individually measure processor core utilization 220, 222, 224 by each of the plurality of hardware threads 226, 228, 230.

An exemplary implementation comprises an operating system (OS) scheduler 118 of an OS 116 for a processor core 104 that makes a determination of utilization of the processor core 104 by a plurality of hardware threads 226, 228, 230 over a time interval through a division of a length of the time interval by a total count of the plurality of hardware threads 226, 228, 230.

The time interval occurs between successive OS context switches of the OS 116. Each of the plurality of hardware threads 226, 228, 230 on the OS 116 between the successive OS context switches independently and substantially simultaneously processes a respective set of software threads 238, 240 242. At least one of the sets of software threads 238, 240 242 comprises a plurality of software threads 238, 240 242.

A standard yield occurs when a standard hardware thread does not have a software thread scheduled on the hardware thread, for example, no more tasks are present in the task run queue for the hardware thread. In such a case, the hardware thread enters an idle function in the OS or kernel and spins waiting for something to be put into the task queue. On standard multithreaded or hyperthreaded hardware this means that the one hardware thread that is processing a software thread receives only a fraction, for example, fifty percent in the case of dual hardware threads, of the core resources as the other hardware thread that is spinning in the idle function. The idle hardware thread still consumes the other fifty percent of the core resources basically doing nothing but waiting for work. With yield operations added into the OS idle function, once the hardware thread in the idle function starts executing the yield function, the other hardware thread will start receiving more than fifty percent of the core resources. An exemplary implementation may give the one hardware thread running a software thread on the order of ninety-five percent or more of the CPU resources. Doing this in an example results in breaking and/or reducing the accuracy of the time executing and utilization data collected in the divide by n approach, for example, because the two hardware threads actually have significantly different utilization of the core resource 104. An exemplary approach performs yield start/stop timing and then adds/subtracts this amount from the appropriate execution counters for the hardware threads to obtain, adjust, and/or produce the data. In view of the execution of yield operations, an exemplary implementation tracks the time and updates the execution time counters for the hardware threads.

In an exemplary approach, the plurality of hardware threads 226, 228, 230 comprises at least a first hardware thread and a second hardware thread. The time interval occurs between successive operating system (OS) context switches. The determination of processor core utilization 220, 222, 224 is interpreted as an initial determination of per-thread processor core utilization 220, 222, 224 over the time interval. Multithreaded hardware yield operations from the first hardware thread to the second hardware thread between the successive OS context switches are effected. A determination of a duration of the multithreaded hardware yield operations is made through subtraction of an initiation time value stored upon initiation of the multithreaded hardware yield operations from a completion time value obtained upon completion of the multithreaded hardware yield operations. The duration of the multithreaded hardware yield operations is subtracted from a core utilization counter between the successive OS context switches for the first hardware thread. The duration of the multithreaded hardware yield operations is added to a core utilization counter between the successive OS context switches for the second hardware thread. The initial determination of per-thread processor core utilization 220, 222, 224 over the time interval is combined with the core utilization counter for the first hardware thread to make a determination of total core utilization between the successive OS context switches by the first hardware thread. The initial determination of per-thread processor core utilization 220, 222, 224 over the time interval is combined with the core utilization counter for the second hardware thread to make a determination of total core utilization between the successive OS context switches by the second hardware thread.

Multithreaded hardware yield operations from the second hardware thread to the first hardware thread between the successive OS context switches are effected. A determination of a duration of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread is made through subtraction of an initiation time value stored upon initiation of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread, from a completion time value obtained upon completion of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread. The duration of the multithreaded hardware yield operations is subtracted from the second hardware thread to the first hardware thread, from the core utilization counter between the successive OS context switches for the second hardware thread. The duration of the multithreaded hardware yield operations from the second hardware thread is added to the first hardware thread to the core utilization counter between the successive OS context switches for the first hardware thread. The initial determination of per-thread processor core utilization 220, 222, 224 over the time interval is combined with the core utilization counter for the first hardware thread to make a determination of total core utilization between the successive OS context switches by the first hardware thread. The initial determination of per-thread processor core utilization 220, 222, 224 over the time interval is combined with the core utilization counter for the second hardware thread to make a determination of total core utilization between the successive OS context switches by the second hardware thread.

An exemplary implementation comprises an operating system (OS) scheduler 118 of an OS 116 for a processor core 104 that upon execution of a yield operation of the processor core between successive OS context switches of the OS 116 by a first hardware thread to a second hardware thread of a plurality of hardware threads 226, 228, 230 on the OS: subtracts from a core utilization counter for the first hardware thread a duration of the yield operation of the processor core between the successive OS context switches; and adds to a core utilization counter for the second hardware thread the duration of the yield operation of the processor core between the successive OS context switches.

The OS scheduler 118 upon execution of a yield operation of the processor core between successive OS context switches of the OS 116 by the second hardware thread to the first hardware thread: subtracts from the core utilization counter for the second hardware thread a duration of the yield operation of the processor core between the successive OS context switches by the second hardware thread to the first hardware thread; and adds to the core utilization counter for the first hardware thread the duration of the yield operation of the processor core between the successive OS context switches by the second hardware thread to the first hardware thread.

The OS scheduler 118 comprises a running execution time counter 204, 208. Upon initiation of execution of the yield operation to the second hardware thread the first hardware thread stores an initiation time value of the running execution time counter 204, 208. Upon completion of execution of the yield operation to the second hardware thread the first hardware thread subtracts the initiation time value from a completion time value to make a determination of the duration of the yield operation.

The OS scheduler 118 upon execution of a yield operation of the processor core 104 between successive OS context switches of the OS 116 by the second hardware thread to the first hardware thread: subtracts from the core utilization counter for the second hardware thread a duration of the yield operation of the processor core 104 between the successive OS context switches by the second hardware thread to the first hardware thread; and adds to the core utilization counter for the first hardware thread the duration of the yield operation of the processor core 104 between the successive OS context switches by the second hardware thread to the first hardware thread. Upon initiation of execution of the yield operation to the first hardware thread the second hardware thread stores an initiation time value of the running execution time counter. Upon completion of execution of the yield operation to the first hardware thread the second hardware thread subtracts the initiation time value from a completion time value to make a determination of the duration of the yield operation to the first hardware thread.

The OS scheduler 118 employs a running execution time counter 204, 208 to make a determination of a length of a time interval between successive OS context switches. The OS scheduler 118 makes an initial determination of utilization of the processor core by the plurality of hardware threads 226, 228, 230 over the time interval through division of the length of the time interval by a total count of the plurality of hardware threads 226, 228, 230 on the processor core. Upon initiation of execution of the yield operation to the second hardware thread the first hardware thread stores an initiation time value of the running execution time counter 204, 208. Upon completion of execution of the yield operation to the second hardware thread the first hardware thread subtracts the initiation time value from a current time value of the running execution time counter 204, 208 to make a determination of the duration of the yield operation. The OS scheduler 118 combines a per-thread result of the initial determination of utilization of the processor core 104 with the core utilization counter for the first hardware thread to make a determination of total core utilization between the successive OS context switches by the first hardware thread. The OS scheduler 118 combines the per-thread result of the initial determination of utilization of the processor core 104 with the core utilization counter for the second hardware thread to make a determination of total core utilization between the successive OS context switches by the second hardware thread.

The first hardware thread executes a multithreaded hardware yield operation of the processor core 104 to effect the utilization yield from the first hardware thread to the second hardware thread between the successive OS context switches of the OS 116. Each of the plurality of hardware threads 226, 228, 230 on the OS 116 between the successive OS context switches independently processes at least a respective software thread. Each of the plurality of hardware threads 226, 228, 230 on the OS 116 between the successive OS context switches independently and substantially simultaneously processes a respective set of software threads 238, 240 242, wherein at least one of the sets of software threads 238, 240 242 comprises a plurality of software threads 238, 240 242.

The plurality of hardware threads 226, 228, 230 comprises at least a first hardware thread and a second hardware thread, wherein the time interval occurs between successive OS context switches of the OS 116. The OS scheduler 118 interprets the determination of processor core utilization 220, 222, 224 as an initial determination of per-thread processor core utilization 220, 222, 224 over the time interval. The OS scheduler 118 makes a determination of a duration of multithreaded hardware yield operations from the first hardware thread to the second hardware thread between the successive OS context switches, through subtraction of an initiation time value stored upon initiation of the multithreaded hardware yield operation from a current time value obtained upon completion of the multithreaded hardware yield operations. The duration of the multithreaded hardware yield operations between the successive OS context switches is subtracted from a core utilization counter for the first hardware thread. The duration of the multithreaded hardware yield operations between the successive OS context switches is added to a core utilization counter for the second hardware thread. The OS scheduler 118 combines the initial determination of per-thread processor core utilization 220, 222, 224 over the time interval with the core utilization counter for the first hardware thread to make a determination of total core utilization between the successive OS context switches by the first hardware thread. The OS scheduler 118 combines the initial determination of per-thread processor core utilization 220, 222, 224 over the time interval with the core utilization counter for the second hardware thread to make a determination of total core utilization between the successive OS context switches by the second hardware thread.

The OS scheduler 118 makes a determination of a duration of multithreaded hardware yield operations from the second hardware thread to the first hardware thread between the successive OS context switches, through subtraction of an initiation time value stored upon initiation of the multithreaded hardware yield operation from the second hardware thread to the first hardware thread, from a current time value obtained upon completion of the multithreaded hardware yield operations. The duration of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread between the successive OS context switches is subtracted from the core utilization counter for the second hardware thread. The duration of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread between the successive OS context switches is added to the core utilization counter for the first hardware thread. The OS scheduler 118 combines the initial determination of per-thread processor core utilization 220, 222, 224 over the time interval with the core utilization counter for the first hardware thread to make a determination of total core utilization between the successive OS context switches by the first hardware thread. The OS scheduler 118 combines the initial determination of per-thread processor core utilization 220, 222, 224 over the time interval with the core utilization counter for the second hardware thread to make a determination of total core utilization between the successive OS context switches by the second hardware thread.

An implementation of the apparatus 100 in an example comprises a plurality of components such as one or more of electronic components, mechanical components, hardware components, and/or computer software components. A number of such components can be combined or divided in an implementation of the apparatus 100. An exemplary component of an implementation of the apparatus 100 employs and/or comprises a set and/or series of computer instructions written in or implemented with any of a number of programming languages, as will be appreciated by those skilled in the art.

An implementation of the apparatus 100 in an example encompasses an article. The article comprises one or more computer-readable signal-bearing media. The article comprises means in the one or more media for one or more exemplary and/or desirable functions, approaches, and/or procedures.

An implementation of the apparatus 100 in an example employs one or more computer readable signal bearing media. A computer-readable signal-bearing medium in an example stores software, firmware and/or assembly language for performing one or more portions of one or more implementations. An example of a computer-readable signal bearing medium for an implementation of the apparatus 100 comprises the recordable data storage medium of the memory 106 and/or storage 108. A computer-readable signal-bearing medium for an implementation of the apparatus 100 in an example comprises one or more of a magnetic, electrical, optical, biological, and/or atomic data storage medium. For example, an implementation of the computer-readable signal-bearing medium comprises one or more floppy disks, magnetic tapes, CDs, DVDs, hard disk drives, and/or electronic memory. In another example, an implementation of the computer-readable signal-bearing medium comprises a modulated carrier signal transmitted over a network comprising or coupled with an implementation of the apparatus 100, for instance, one or more of a telephone network, a local area network (“LAN”), a wide area network (“WAN”), the Internet, and/or a wireless network.

The steps or operations described herein are examples. There may be variations to these steps or operations without departing from the spirit of the invention. For example, the steps may be performed in a differing order, or steps may be added, deleted, or modified.

Although exemplary implementation of the invention has been depicted and described in detail herein, it will be apparent to those skilled in the relevant art that various modifications, additions, substitutions, and the like can be made without departing from the spirit of the invention and these are therefore considered to be within the scope of the invention as defined in the following claims. 

1. A method, comprising the step of: making a determination of processor core utilization by a plurality of hardware threads over a time interval through a division of a length of the time interval by a total count of the plurality of hardware threads.
 2. The method of claim 1, wherein one or more hardware thread context switches among two or more of the plurality of hardware threads occur over the time interval, wherein the step of making the determination of processor core utilization comprises the step of: interpreting a result of the division of the time interval by the total count of the plurality of hardware threads as a per-thread processor core utilization.
 3. The method of claim 1, wherein the total count comprises a total count of the plurality of hardware threads on a single processor core, wherein one or more hardware thread context switches for utilization of the single processor core occur among two or more of the plurality of hardware threads over the time interval, wherein the step of making the determination of processor core utilization comprises the step of: making a determination of utilization of the single processor core by the plurality of hardware threads over the time interval through the division of the time interval by the total count of the plurality of hardware threads.
 4. The method of claim 1, wherein the plurality of hardware threads comprises at least a first hardware thread and a second hardware thread of two hardware threads on a single processor core, wherein the step of making the determination of processor core utilization comprises the step of: making a determination of utilization of the single processor core by the two hardware threads over the time interval through division of the time interval by two; the method further comprising the steps of: processing at least a first software thread independently by the first hardware thread during the time interval; and processing at least a second software thread independently by the second hardware thread during the time interval.
 5. The method of claim 1, wherein the total count comprises a total count of the plurality of hardware threads on an operating system (OS) for a single processor core, wherein the time interval occurs between successive OS context switches of the OS, wherein one or more hardware thread context switches for utilization of the single processor core occur among two or more of the plurality of hardware threads over the time interval, wherein the step of making the determination of processor core utilization comprises the step of: making a determination of processor core utilization by the plurality of hardware threads between the successive OS context switches and over the one or more hardware thread context switches through a division of the length of time between the successive OS context switches by the total count of the plurality of hardware threads on the OS of the single processor core.
 6. The method of claim 1, wherein one or more hardware thread context switches among two or more of the plurality of hardware threads occur over the time interval, wherein the step of making the determination of processor core utilization comprises the step of: dividing the length of the time interval by the total count of the plurality of hardware threads to make the determination of processor core utilization as a substitute for employment of one or more absent, unselected, and/or unavailable per-hardware thread interval time counters that would otherwise be employable to individually measure processor core utilization by each of the plurality of hardware threads.
 7. The method of claim 1, wherein the plurality of hardware threads comprises at least a first hardware thread and a second hardware thread, wherein the time interval occurs between successive operating system (OS) context switches, wherein the step of making the determination of processor core utilization comprises the step of: interpreting the determination of processor core utilization as an initial determination of per-thread processor core utilization over the time interval; the method further comprising the steps of: effecting multithreaded hardware yield operations from the first hardware thread to the second hardware thread between the successive OS context switches; making a determination of a duration of the multithreaded hardware yield operations through subtraction of an initiation time value stored upon initiation of the multithreaded hardware yield operations from a completion time value obtained upon completion of the multithreaded hardware yield operations; subtracting the duration of the multithreaded hardware yield operations from a core utilization counter between the successive OS context switches for the first hardware thread; adding the duration of the multithreaded hardware yield operations to a core utilization counter between the successive OS context switches for the second hardware thread; combining the initial determination of per-thread processor core utilization over the time interval with the core utilization counter for the first hardware thread to make a determination of total core utilization between the successive OS context switches by the first hardware thread; and combining the initial determination of per-thread processor core utilization over the time interval with the core utilization counter for the second hardware thread to make a determination of total core utilization between the successive OS context switches by the second hardware thread.
 8. The method of claim 7, further comprising the steps of: effecting multithreaded hardware yield operations from the second hardware thread to the first hardware thread between the successive OS context switches; making a determination of a duration of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread through subtraction of an initiation time value stored upon initiation of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread, from a completion time value obtained upon completion of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread; subtracting the duration of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread, from the core utilization counter between the successive OS context switches for the second hardware thread; adding the duration of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread to the core utilization counter between the successive OS context switches for the first hardware thread; combining the initial determination of per-thread processor core utilization over the time interval with the core utilization counter for the first hardware thread to make a determination of total core utilization between the successive OS context switches by the first hardware thread; and combining the initial determination of per-thread processor core utilization over the time interval with the core utilization counter for the second hardware thread to make a determination of total core utilization between the successive OS context switches by the second hardware thread.
 9. An apparatus, comprising: an operating system (OS) scheduler of an OS for a processor core that upon execution of a yield operation of the processor core between successive OS context switches of the OS by a first hardware thread to a second hardware thread of a plurality of hardware threads on the OS: subtracts from a core utilization counter for the first hardware thread a duration of the yield operation of the processor core between the successive OS context switches; and adds to a core utilization counter for the second hardware thread the duration of the yield operation of the processor core between the successive OS context switches.
 10. The apparatus of claim 9, wherein the OS scheduler upon execution of a yield operation of the processor core between successive OS context switches of the OS by the second hardware thread to the first hardware thread: subtracts from the core utilization counter for the second hardware thread a duration of the yield operation of the processor core between the successive OS context switches by the second hardware thread to the first hardware thread; and adds to the core utilization counter for the first hardware thread the duration of the yield operation of the processor core between the successive OS context switches by the second hardware thread to the first hardware thread.
 11. The apparatus of claim 9, wherein the OS scheduler comprises a running execution time counter, wherein upon initiation of execution of the yield operation to the second hardware thread the first hardware thread stores an initiation time value of the running execution time counter, wherein upon completion of execution of the yield operation to the second hardware thread the first hardware thread subtracts the initiation time value from a completion time value to make a determination of the duration of the yield operation.
 12. The apparatus of claim 11, wherein the OS scheduler upon execution of a yield operation of the processor core between successive OS context switches of the OS by the second hardware thread to the first hardware thread: subtracts from the core utilization counter for the second hardware thread a duration of the yield operation of the processor core between the successive OS context switches by the second hardware thread to the first hardware thread; and adds to the core utilization counter for the first hardware thread the duration of the yield operation of the processor core between the successive OS context switches by the second hardware thread to the first hardware thread; wherein upon initiation of execution of the yield operation to the first hardware thread the second hardware thread stores an initiation time value of the running execution time counter, wherein upon completion of execution of the yield operation to the first hardware thread the second hardware thread subtracts the initiation time value from a completion time value to make a determination of the duration of the yield operation to the first hardware thread.
 13. The apparatus of claim 9, wherein the OS scheduler employs a running execution time counter to make a determination of a length of a time interval between successive OS context switches, wherein the OS scheduler makes an initial determination of utilization of the processor core by the plurality of hardware threads over the time interval through division of the length of the time interval by a total count of the plurality of hardware threads on the processor core; wherein upon initiation of execution of the yield operation to the second hardware thread the first hardware thread stores an initiation time value of the running execution time counter, wherein upon completion of execution of the yield operation to the second hardware thread the first hardware thread subtracts the initiation time value from a current time value of the running execution time counter to make a determination of the duration of the yield operation; wherein the OS scheduler combines a per-thread result of the initial determination of utilization of the processor core with the core utilization counter for the first hardware thread to make a determination of total core utilization between the successive OS context switches by the first hardware thread; wherein the OS scheduler combines the per-thread result of the initial determination of utilization of the processor core with the core utilization counter for the second hardware thread to make a determination of total core utilization between the successive OS context switches by the second hardware thread.
 14. The apparatus of claim 9, wherein the first hardware thread executes a multithreaded hardware yield operation of the processor core to effect the utilization yield from the first hardware thread to the second hardware thread between the successive OS context switches of the OS.
 15. The apparatus of claim 9, wherein each of the plurality of hardware threads on the OS between the successive OS context switches independently processes at least a respective software thread.
 16. The apparatus of claim 9, wherein each of the plurality of hardware threads on the OS between the successive OS context switches independently and substantially simultaneously processes a respective set of software threads, wherein at least one of the sets of software threads comprises a plurality of software threads.
 17. An apparatus, comprising: an operating system (OS) scheduler of an OS for a processor core that makes a determination of utilization of the processor core by a plurality of hardware threads over a time interval through a division of a length of the time interval by a total count of the plurality of hardware threads.
 18. The apparatus of claim 17, wherein the time interval occurs between successive OS context switches of the OS, wherein each of the plurality of hardware threads on the OS between the successive OS context switches independently and substantially simultaneously processes a respective set of software threads, wherein at least one of the sets of software threads comprises a plurality of software threads.
 19. The apparatus of claim 17, wherein the plurality of hardware threads comprises at least a first hardware thread and a second hardware thread, wherein the time interval occurs between successive OS context switches of the OS; wherein the OS scheduler interprets the determination of processor core utilization as an initial determination of per-thread processor core utilization over the time interval; wherein the OS scheduler makes a determination of a duration of multithreaded hardware yield operations from the first hardware thread to the second hardware thread between the successive OS context switches, through subtraction of an initiation time value stored upon initiation of the multithreaded hardware yield operation from a current time value obtained upon completion of the multithreaded hardware yield operations; wherein the duration of the multithreaded hardware yield operations between the successive OS context switches is subtracted from a core utilization counter for the first hardware thread; wherein the duration of the multithreaded hardware yield operations between the successive OS context switches is added to a core utilization counter for the second hardware thread; wherein the OS scheduler combines the initial determination of per-thread processor core utilization over the time interval with the core utilization counter for the first hardware thread to make a determination of total core utilization between the successive OS context switches by the first hardware thread; and wherein the OS scheduler combines the initial determination of per-thread processor core utilization over the time interval with the core utilization counter for the second hardware thread to make a determination of total core utilization between the successive OS context switches by the second hardware thread.
 20. The apparatus of claim 19, wherein the OS scheduler makes a determination of a duration of multithreaded hardware yield operations from the second hardware thread to the first hardware thread between the successive OS context switches, through subtraction of an initiation time value stored upon initiation of the multithreaded hardware yield operation from the second hardware thread to the first hardware thread, from a current time value obtained upon completion of the multithreaded hardware yield operations; wherein the duration of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread between the successive OS context switches is subtracted from the core utilization counter for the second hardware thread; wherein the duration of the multithreaded hardware yield operations from the second hardware thread to the first hardware thread between the successive OS context switches is added to the core utilization counter for the first hardware thread; wherein the OS scheduler combines the initial determination of per-thread processor core utilization over the time interval with the core utilization counter for the first hardware thread to make a determination of total core utilization between the successive OS context switches by the first hardware thread; and wherein the OS scheduler combines the initial determination of per-thread processor core utilization over the time interval with the core utilization counter for the second hardware thread to make a determination of total core utilization between the successive OS context switches by the second hardware thread. 